Direct Cu Bonding: 3D-IC Integration 1

Researchers at Tohoku University in Japan have developed a direct Cu bonding technology that temporarily adheres 100-μm-cubed blue μ LEDs on a photosensitive resin, which allows a lot of dielets to be stacked on thin 3D-IC chiplets without the need for thermal compression bonding. The researchers used semi-additive plating (SAP) bonding and identified three key technologies used to solve yield issues. Coplanarity enhancement eliminates Cu bridges, while the use of sidewalls insulated by room-temperature ozone-ethylene-radical (OER)-SiO2-CVD, and partial seed pre-etching both increase yield. Further design optimization is needed, but the researchers discuss a superior prospect for yield enhancement towards nearly 100%. The research paper can be found in IEEE Electron Device Letters.

Researchers at Tohoku University in Japan have published a technical paper titled “Room-Temperature Direct Cu Semi-Additive Plating (SAP) Bonding for Chip-on-Wafer 3D Heterogeneous Integration With μLED”. The paper discusses a direct Cu bonding technology used to integrate heterogeneous dielets based on a chip-on-wafer configuration, without the need for thermal compression bonding. Using semi-additive plating (SAP) bonding, researchers have managed to temporarily adhere 100-μm-cubed blue μ LEDs on a photosensitive resin, enabling a lot of dielets to be stacked on thin 3D-IC chiplets. The paper identifies three key technologies used to solve the yield issues of SAP bonding. The first is coplanarity enhancement, which eliminates Cu bridges grown to a small gap between the μ LEDs and photosensitive resin. The second technology is the use of sidewalls insulated by room-temperature ozone-ethylene-radical (OER)-SiO2-CVD, and the third is partial seed pre-etching which increases yield. While further design optimization is required, researchers discuss a superior prospect for yield enhancement towards nearly 100%.

The research paper was published in January 2023, and can be found in IEEE Electron Device Letters. According to the paper, fully integrated module implementation with the 3D-ICs will be the next stage.

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